This application claims priority to International Application No. PCT/DE00/03219 which was published in the German language on Sept. 15, 2000.
The invention relates to a circuit having a clock signal with a frequency synchronous with a reference clock signal.
In digital communications systems, individual communications system components require an accurate system clock for synchronizing interchange of communications data. Normally, highly accurate reference clock signals are supplied to individual communications system components for this purpose, e.g. via the public network. Generally, the reference clock signals supplied do not directly provide clock control for a communications system component, but rather are routed to a phase locked loop in which system clock signals are formed and transmitted to individual assemblies.
Since interference-free transmission of an external reference clock signal cannot be guaranteed at all times, a communications system component is often provided with a dedicated highly stable reference clock source which, in the event of the external reference clock signal disappearing, is used to stabilize the clock generator via a second phase locked loop.
Such a circuit arrangement is known from European patent application 0 262 481, for example. This circuit arrangement contains a reference reception part which receives the external reference clock signals and is connected to a first input of a first phase comparison device. The output of the first phase comparison device is routed via an integration device and a filter whose output can be connected to a downstream voltage controlled oscillator using a switching element. The synchronous-frequency clock signals formed in the voltage controlled oscillator are routed from the latter""s output both to an output of the circuit arrangement and to a second input of the first phase comparison device.
The known circuit arrangement also contains a highly stable reference clock source whose output is connected to a first input of a second phase comparison device. The second input of this second phase comparison device is likewise connected to the output of the voltage controlled oscillator. The output of the second phase comparison device can be connected either to an additional filter or to a minuend input of a subtraction element using a further switching element. The output of the subtraction element, to whose subtrahend input the output of the additional filter is connected, is connected to another input of the switching element via a further filter.
The known circuit arrangement thus contains two phase locked loops, the first phase locked loop being controlled by the external reference clock signals, and the second phase locked loop being controlled by the reference clock signals from the highly stable reference clock source. Normally, the voltage controlled oscillator is synchronized with the supplied external reference clock signals. If the external reference clock signals disappear or if prescribed phase differences are exceeded, there is a switch to the highly stable reference clock source. In the additional filter, during synchronization by the external reference clock signals, the discrepancies between the synchronous-frequency clock signals and the reference clock signals from the highly stable reference clock source are gathered and correction adjustment information is formed. After switching to the highly stable reference clock source, the subtraction element is used to include this correction adjustment information in the formation of adjustment information for the voltage controlled oscillator.
However, this circuit arrangement has the problem that, to avoid an excessively long regulation delay, the frequency of the highly stable reference clock source should be comparatively high. A high clock frequency also results in a comparatively high current consumption, however, which means that such a circuit arrangement is not very suitable for battery operation. In addition, such a circuit arrangement is provided with switching means in order to detect cyclically occurring phase overflows in the second phase comparison device. In this context, phase overflow denotes when a phase difference of 360 degrees is exceeded. Such phase overflows occur cyclically if the frequency of the reference clock source and the frequency of the voltage controlled oscillator, synchronized with the external reference clock signal, differ from one another systematically, possibly after they have each passed through a frequency divider.
In one embodiment of the invention, there is a circuit arrangement for producing a clock signal whose frequency is synchronous with that of reference clock signals which has an improved regulation characteristic, in particular when a reference clock signal having a comparatively low clock frequency is supplied.
The circuit arrangement includes, for example, an oscillator whose clock frequency, in a first operating mode of the circuit arrangement, synchronized with a supplied, first reference clock signal using a first phase locked loop which comprises a first phase comparison device. In addition, a phase control element and a second phase comparison device are provided which are used in the first operating mode to detect a discrepancy between a supplied, second reference clock signal and the synchronous-frequency clock signal from the oscillator and to form phase correction information. In a second operating mode of the circuit arrangement, e.g. if the first reference clock signal disappears, the oscillator is no longer synchronized using the first reference clock signal, but rather using the second reference clock signal. Such a second operating mode is often also referred to as xe2x80x9chold-over modexe2x80x9d. In this case, the phase correction information formed in the first operating mode is brought into the phase control. This is done by virtue of a phase control element inserting or removing clock phases in the clock signal from the oscillator on the basis of the phase correction information before phase comparison with the second reference clock signal.
Correction of the oscillator phase or oscillator frequency before phase comparison with the second reference clock signal makes it easy to prevent cyclically occurring phase overflows during phase comparison when there is a systematic discrepancy between the oscillator clock signal, whose frequency is synchronous with that of the first reference clock signal, and the second reference clock signal.
One advantage of the circuit arrangement provides very good regulation characteristic and short regulation time constants which are ensured, in particular, even for a comparatively low-frequency second reference clock signal. The production of low-frequency reference clock signals generally requires less power than the production of higher-frequency reference clock signals, which means that the circuit arrangement in conjunction with a low-frequency reference clock generator is also well suited to battery operation. The good regulation characteristic is a consequence of the phase correction by the phase control element being applied to the clock signal from the oscillator. Since the clock signal from the oscillator normally has a much higher frequency than the second reference clock signal, removal or insertion of individual clock phases in the clock signal from the oscillator makes it possible to control the frequency of this clock signal very precisely before phase comparison. In particular, this causes only very low phase and pulse jitter.
Another advantage of the inventive circuit arrangement is that no processor is required for implementing it. Instead, the circuit arrangement can be implemented using an inexpensive ASIC chip (Application Specific Integrated Circuit), for example.
In one aspct of the invention, the output of the first phase comparison device can be connected to the frequency control input of the oscillator via a switching element, such as a transistor, a logic gate or a multiplex device. This switching element can be actuated such that it is on in the first operating mode of the circuit arrangement and is off in the second operating mode.
Connected upstream of the frequency control input of the oscillator there may also be a filter, such as a simple low-pass filter or a xe2x80x9cP, PI or PID filterxe2x80x9d, for integrating frequency control signals supplied to the oscillator. The frequency control input of the oscillator may often also perform such a filter function itself.
In addition, a memory can be provided which keeps the phase correction information formed in the first operating mode stored in it for as long as the circuit arrangement is in the second operating mode. In the second operating mode, the insertion and removal of clock phases is then controlled in the phase control element on the basis of the stored phase correction information.
To be able to compare two different clock signals using a phase comparison device, it is generally necessary for the clock signals which are to be compared to have the same nominal frequency. To compare clock signals having different nominal frequencies, these clock signals can respectively be supplied to the phase comparison device via a frequency divider. In this case, the division factor of a respective frequency divider is proportioned such that the divided nominal frequencies applied to the inputs of the phase comparison device are the same.
In accordance with one advantageous embodiment of the invention, a detector device can be provided which can be used to identify whether the first reference clock signal is present. An output of the detector device can be connected to one or more switching elements for controlling and/or changing over the operating mode.
In accordance with another advantageous embodiment of the invention, the regulating device can have an up/down counter whose counting direction is dependent on the output signal from the second phase comparison device. The up/down counter can be actuated, by way of example, such that its counter reading is either incremented or decremented at prescribed times, e.g. in each case on the positive or negative edges of the second reference clock signal, depending on whether the phase difference established is positive or negative. If the phases are equal, the counter reading can remain the same.
In addition, a phase control element controller having a counting register can be provided, the counting register being able to be loaded with the counter reading from the up/down counter as a counting preset. In this context, the counting register can be advanced starting from the counting preset, for example with timing prescribed by a clock signal, in order to prompt insertion or removal of a clock phase in the phase control element when a prescribed counting marker is reached.
In addition, the counting register can be split into a first register part for more significant bits and a second register part for less significant bits, with a counting frequency used to advance the second register part being determined by the content of the first register part. This functional isolation of the register parts allows a very wide control range to be achieved even when the length of the counting register or of the up/down counter is short. In this context, regulation is more accurate the lower the value of the more significant bits of the counting preset which determine the counting frequency, i.e. the less the clock signals which are to be compared by the second phase comparison device differ from one another.
In accordance with another advantageous embodiment of the invention, another phase control element, controlled by the regulating device, for deriving a further synchronous-frequency clock signal from the second reference clock signal can be provided. This allows a synchronous-frequency clock signal to be provided for a meter application, for example.